A switched network usually includes multiple switch nodes (also referred to as “nodes”) which are connected by communication links and arranged in a topology referred to in the art as a “mesh network”. Within the mesh network, user traffic can be transported between any two locations using predefined connections specifying particular links and/or switch nodes for conveying the user traffic.
The switch nodes in the mesh network are each provided with a control module. The control modules of the switch nodes function together to aid in the control and management of the mesh networks. The control modules can run a variety of protocols for conducting the control and management of the mesh networks. One prominent protocol is referred to in the art as “Generalized Multiprotocol Label Switching (GMPLS)”.
Lowering the cost of a node often involves re-designing the hardware of the control module using low cost electronic components but keeping the system software unchanged. However, the programming requirement and the command set in the new, cost-reduced hardware may be different from the previous hardware for which the software has been originally developed. Replacing a component of the control module typically requires that either the new component or other components in the control module be reprogrammed to use the same system software.
Alternatively, some systems have translated commands from the software into a corresponding command for the new hardware. A general method to identify the received byte-sequence will be described hereinafter. In the general method, there are M numbers of stored sequences and each sequence is N-byte long. The byte [aij] is the j-th byte of sequence number i. The byte-sequence for a particular mode is unique and predetermined. The known byte-sequences for all the modes are stored in the hardware. The received byte-sequence is, say, [ax0, ax1, . . . , ax(N−1)] where x ε {0, (M−1)}. Identification of the byte-sequence is achieved by determining the value of x in the FPGA. At first, the received byte-sequence is saved in the RNV memory in the FPGA. Then, the received sequence of bytes is compared with the M numbers of stored sequences by comparing all the bytes of the sequence to declare a match. Thus the received sequence, x, is determined. This technique requires N-byte R/W memory cells in the FPGA to save all the received bytes, ax0, ax1, . . . , ax(N−1). It also requires comparison of the entire sequence with all the stored sequences to determine a match. M numbers of digital comparators are required, each comparator being N-byte long. So this technique is resource intensive and inefficient and may not be suitable for implementation in FPGA with limited resources such as the memory and logic blocks.
Apparatuses and methods are needed to enable hardware components having a command set that differs from the command set utilized by the software to be used to update and/or make new control modules without having to update and/or reprogram the command set of the system software while reducing resource usage and cost. It is to such a system and method that the present disclosure is directed.